M.Sc. Jan Moritz Joseph

M.Sc. Jan Moritz Joseph

Lehrstuhl Hardware-nahe Technische Informatik
Universitätsplatz 2, 39016, Magdeburg, Building 09, Room 418

M.Sc. Jan Moritz Joseph

Lehrstuhl Hardware-nahe Technische Informatik
Universitätsplatz 2, 39016, Magdeburg, G09-418

Curriculum Vitae

NoC BuzzerJan Moritz Joseph was born in Berlin, Germany, in 1990. He received the B.Sc. degree in Medical Engineering in 2011 and the M.Sc. degree in Informatics in 2014 from the Universität zu Lübeck. From 2008 to 2014, he was a scholarship holder of The German National Merit Foundation. He is currently working on a doctorate degree as a research assistant at the Otto-von-Guericke-Universität Magdeburg, Germany, in the Institute for Information and Communication Technology.

He has been investigating Network-on-Chips as these are scalable communication infrastructures for modern multi-core systems. Two of his areas of particular interest are the prioritization of semi-static data streams in on-Chip networks and asymmetric 3D-Network-on-Chips.

Research Focus

  • Network-on-Chips (NoCs)
  • Latency Reductions in NoCs via adaptive prioritization of semi-static data streams
  • Asymmetric 3D-Network-on-Chips (A-3D-NoCs) targeting heterogeneous 3D-System-on-Chips

Projects

  • DFG-Project "Erkennung und adaptive Priorisierung von semi-statischen Datenströmen und von Verkehrsstrommustern in Network-on-Chips" ("Detection and adaptive prioritization of semi-static data streams and data pattern in Network-on-Chips")
  • DFG-Project "Technology-aware Asymmetric 3D-Interconnect Architectures: Templates and Design Methods"
  • Asymmetric 3D-Network-on-Chips
  • NoC Simulator for A-3D-NoCs, see on Github

Software

I am currently maintaining the code related to our NoC projects. This covers the simualtor ratatoskr and optimization tools. I kindly refer to https://github.com/jmjos for the source code.

Student assistance, projects, thesis

If you are interested, please refer to our site or contact me.

Publications

Full Publications
2017 Jan Moritz Joseph, Morten Mey, Kristian Ehlers, Christopher Blochwitz, Tobias Winker, Thilo Pionteck: Design Space Exploration for a Hardware-accelerated Embedded Real-Time Pose Estimation using Vivado HLS, Reconfig, Cancun, Mexico, 2017.
2017 Tobias Drewes, Jan Moritz Joseph, Thilo Pionteck: An FPGA-based Prototyping Framework for Networks-on-Chip, Reconfig, Cancun, Mexico, 2017.
2017 Christopher Blochwitz, Raphael Klink, Jan Moritz Joseph, Thilo Pionteck: Continuous Live-Tracing as Debugging Approach on FPGAs, Reconfig, Cancun, Mexico, 2017.
2017 Jan Moritz Joseph, Lennart Bamberg, Sven Wrieden, Dominik Ermel, Alberto Garcia-Oritz, Thilo Pionteck: Design Method for Asymmetric 3D-Interconnect Architectures with High Level Models, ReCoSoC, Madrid, Spain, 2017.
2017 Jan Moritz Joseph, Christopher Blochwitz, Alberto García-Ortiz, Thilo Pionteck: Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs, MICPRO 2460, 2017.
2016 Christopher Blochwitz, Julian Wolff, Jan Moritz Joseph, Stefan Werner, Dennis Heinrich, Sven Groppe, Thilo Pionteck: Hardware-accelerated Radix-Tree based string sorting for Big Data applications, ARCS 2017.
2016 Jan Moritz Joseph, Tobias Winker, Kritian Ehlers, Christopher Blochwitz, Thilo Pionteck: Hardware-Accelerated Pose Estimation for Embedded Systems using Vivado HLS , Reconfig, Cancun, Mexiko, 2016. preprint, poster
2016 Jan Moritz Joseph, Sven Wrieden, Christopher Blochwitz, Alberto García-Ortiz, Thilo Pionteck: A Simulation Environment for Design Space Exploration for Asymmetric 3D-Network-on-Chip, 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), Tallinn, 2016. presentation, preprint
2016 Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck: Adaptive Allocation of Default Router Paths in Network-on-Chips for Latency Reduction, 2016 International Conference on High Performance Computing & Simulation (HPCS), Innsbruck, 2016. presentation, preprint
2015 Jan Moritz Joseph, Christopher Blochwitz, Alberto García-Ortiz, Thilo Pionteck: Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs, Nordic Circuits and Systems Conference (NORCAS), Oslo, 2015. preprint
2015 Christopher Blochwitz, Jan Moritz Joseph, Rico Backasch, Stefan Werner, Dennis Heinrich, Sven Groppe, Thilo Pionteck; An optimized Radix-Tree for hardware-accelerated index generation for Semantic Web Databases, Reconfig, Cancun, Mexiko, 2015
2015 Jan Moritz Joseph, Thilo Pionteck; A Cycle-Accurate Network-on-Chip Simulator with Support for Abstract Task Graph, International Symposium on System-on-Chip, Tampere, 2014. presentation, preprint
Posters and Minor Conference Publications
  • Jan Moritz Joseph, Philipp Forster, Matthias Hudecek; "Digitalisierung von Change Management", 3. Tagung für Führung und Organisation, Berlin, 2016
  • Jan Moritz Joseph, Jens Christian Claussen; "Dynamical model of the scientific process: Knowledge generation embedded in the scientific map of science", DPG Spring Meeting, Regensburg, 2016
  • Jan Moritz Joseph, Matthias Hudecek; "Measurability and Characteristics of Structural Metrics and Business Scores for HR development", DPG Spring Meeting, Regensburg, 2016
  • Jan Moritz Joseph, Jens Christian Claussen; "Modeling the evolution of science in scientific space", DPG Spring Meeting, Berlin, 2015
  • Jan Moritz Joseph, Jens Christian Claussen; "A dynamical author-strategic growth model for the structure of science in scientific space", XXXIV Dynamics Days Europe, Bayreuth, 2014
  • Jan Moritz Joseph, Jens Christian Claussen; "A Dynamical Model of Scientific Collaboration Networks", DPG Spring Meeting, Dresden, 2014

Disclaimer: Preprints are offered in compliance with the IEEE copyright policy: An FAQ on Intellectual Property Rights for IEEE Authors

Diploma supervision:

  • Tobias Winker. Generierung einer Hardwarebeschleunigung zur Gestenerkennung auf einem Xilinx Zynq unter Verwendung von High Level Synthesis. Bachelorarbeit, Universität zu Lübeck, 2016.
  • Morten Mey. Entwurf und Implementierung eines hardwarebeschleunigten Algorithmus zur Gestenerkennung. Masterarbeit, Universität zu Lübeck, 2016.
Publications

2017

Begutachteter Zeitschriftenartikel

Joseph, Jan Moritz;  Blochwitz, Christopher;  García Ortiz, Alberto;  Pionteck, Thilo 

Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs$Jan Moritz Joseph, ChristopherBlochwitz, Alberto García-Ortiz, Thilo Piontecka
In: Microprocessors and microsystems - Amsterdam [u.a.]: Elsevier, Bd. 48.2017, S. 36-47; http://dx.doi.org/10.1016/j.micpro.2016.09.011

Buchbeitrag

Drewes, Tobias;  Joseph, Jan Moritz;  Pionteck, Thilo 

An FPGA-based prototyping framework for networks-on-Chip
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; poster session A]

Blochwitz, Christopher;  Klink, Raphael;  Joseph, Jan Moritz;  Pionteck, Thilo 

Contentious live-tracing as debugging approach on FPGAS
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; General session]

Joseph, Jan Moritz;  Bamberg, Lennart;  Wrieden, Sven;  Ermel, Dominik;  García-Oritz, Alberto;  Pionteck, Thilo 

Design method for asymmetric 3D interconnect architectures with high level models
In: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017): July 12-14, 2017, Madrid, Spain : proceedings - [Piscataway, NJ]: IEEE, insges. 8 S.; http://dx.doi.org/10.1109/recosoc.2017.8016143 ; [Symposium: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2017, Madrid, Spain, July 12-14 2017]

Joseph, Jan Moritz;  Mey, Morten;  Ehlers, Kristian;  Blochwitz, Christopher;  Winker, Tobias;  Pionteck, Thilo 

Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; Poster session B]

Blochwitz, Christopher;  Wolff, Julian;  Joseph, Jan Moritz;  Werner, Stefan;  Heinrich, Dennis;  Groppe, Sven;  Pionteck, Thilo 

Hardware-accelerated radix-tree based string sorting for big data applications
In: Architecture of Computing Systems - ARCS 2017: 30th International Conference, Vienna, Austria, April 3-6, 2017, Proceedings - Cham: Springer International Publishing, S. 47-58 - (Lecture Notes in Computer Science; 10172); http://dx.doi.org/10.1007/978-3-319-54999-6_4 ; [Konferenz: 30th International Conference on Architecture of Computing Systems, ARCS 2017, Vienna, Austria, April 3-6, 2017]

2016

Buchbeitrag

Joseph, Jan Moritz;  Wrieden, Sven;  Blochwitz, Christopher;  Garcia-Oritz, Alberto;  Pionteck, Thilo 

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip
In: 2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoc) : June 27-29, 2016, Tallinn, Estonia. - Piscataway, NJ : IEEE

Joseph, Jan Moritz;  Blochwitz, Christioher;  Pionteck, Thilo 

Adaptive allocation of default router paths in Network-on-Chips for latency reduction
In: 2016 International Conference on High Performance Computing & Simulation (HPCS). - Piscataway, NJ : IEEE

Joseph, Jan Moritz;  Winker, Tobias;  Ehlers, Christian;  Blochwitz, Christopher;  Pionteck, Thilo 

Hardware-accelerated pose estimation for embedded systems using vivado HLS
In: ReConFig : 2016 International Conference on Reconfigurable Computing and FPGAs : November 30 - December 2, Cancun, Mexico. - Piscataway, NJ : IEEE ; [Kongress: 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig, Cancun, Mexico, November 30 - December 2, 2016]

2015

Herausgeberschaft

Joseph, Jan Moritz;  Blochwitz, Christopher;  Pionteck, Thilo;  Garcia-Ortiz, Alberto 

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
In: 2015, S. 1-4, 10.1109/NORCHIP.2015.7364370

2014

Herausgeberschaft

Joseph, Jan Moritz;  Pionteck, Thilo 

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling
In: 2014, S. 1-6, 10.1109/ISSOC.2014.6972440

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