Electronic System Level Modeling (WiSe)
Responsible: Prof.-Dr. Thilo Pionteck
The increasing complexity in the design of digital systems makes it necessary to increase the level of abstraction in circuit design compared to the commonly used Register Transfer Level (RTL) in VHDL or Verilog. In the course of this lecture, Electronic System Level (ESL) design techniques will be presented, which should enable a largely automated synthesis of hardware accelerators at the algorithmic level. Emphases will be on the introduction to the C ++ class library SystemC and the design principle of Transaction Level Modeling. Furthermore, methods are presented with which allow to tranfer C programs into data flow graphs, from which hardware structures can then be created automatically. The main steps of circuit synthesis (scheduling, allocation and binding) are discussed and corresponding algorithms are presented.
For the lecture an exercise is offered in which practical examples can be used to test the different modeling approaches independently.
The topics are in detail:
- Introduction to SystemC
- Simulation mechanisms
- Transaction Level Modeling
- Timing Models
- Data flow modeling and transformation
- Translating C to hardware
Lecture language: English