Electronic System Level Modeling (WiSe)

Responsible: Prof.-Dr. Thilo Pionteck

High Level Design

The increasing complexity in the design of digital systems makes it necessary to increase the level of abstraction in circuit design compared to the commonly used Register Transfer Level (RTL) in VHDL or Verilog. In the course of this lecture, Electronic System Level (ESL) design techniques will be presented, which should enable a largely automated synthesis of hardware accelerators at the algorithmic level. Emphases will be on the introduction to the C ++ class library SystemC and the design principle of Transaction Level Modeling. For the lecture an exercise is offered in which practical examples can be used to test the different modeling approaches independently.

The topics are in detail:

  • Modeling Concepts for Complex Systems (Register Transfer Modeling, Transaction Level Modeling)
  • Modeling Languages ​​(SystemC)
  • Timing Models
  • Design Space Exploration
    • Simulation algorithms
    • Optimization methods
  • Implementation of simulation environments
  • Case study: 3D System-on-Chips

Last Modification: 07.09.2018 - Contact Person:

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