Otto-von-Guericke-Universität Magdeburg


Network-on-Chip (NoC)

Asymmetric 3D-Network-on-Chips (A-3D-NoCs) targeting heterogeneous 3D-System-on-Chips

Area and power savings via buffer reorganization

ArchitectureDelayWe proposed optimizations for asymmetric Network-on-Chip (NoC) router architectures for heterogeneous 3D-System-on-Chips (SoCs). The optimizations cover buffer reorganization among dies and focus on power and area savings. The architectures are compared to conventional, symmetric routers on the bases of synthesizable RTL models. Area savings of 8.3% and power savings of 5.4% for link buffers are achieved while accepting a minor average system performance loss of 2.1% in simulations. We thereby demonstrate the potentials of asymmetric NoC designs for heterogeneous 3D-SoCs. This work was published in 2015 in cooperation with Prof. García-Ortiz's work group at the ITEM (University of Bremen, Germany):

A-3D-NoC Simulation Framework

AbstractionLevelAt the 2016 ReCoSoC in Tallin we presented a comprehensive simulation environment for design space exploration in Asymmetric 3D-Networks-on-chip (A-3D-NoCs) covering the heterogeneity in 3D-System-on-chips (3D-SoCs). A challenging aspect of A-3D-NoC design is the consideration of interwoven parameters of the communication infrastructure and characteristics of the manufacturing technologies. Thus, simultaneous evaluation of multiple design metrics is mandatory. Our simulation environment consists of three parts. First, it comprises a NoC simulator that supports a multitude of different manufacturing technologies, router architectures, and network topologies within a single design. As a key feature, the NoC and technologies parameters per chip layer are fully configurable during simulation runtime permitting flexible and fast evaluation. Second, a central reporting tool facilitates system analysis on different abstraction levels. Third, the evaluation tool provides various synthetic and real-world based benchmarks. Thus, our tool allows for an incremental approach to systematically explore the A-3D-NoC's design space.

ToolFlowFinalOn the right-hand side the tool flow of our framework is shown. It also comprises the three central parts of the environment, the NoC simulator, the benchmarking tool, and the reporting tool. It enables an incremental approach during design space exploration. In this method, the level of detail is gradually raised to tackle the difficulties in A-3D-NoC design targeting heterogeneous 3D-SoCs. The design space is iteratively explored with different sets of fixed and variable parameters, in which the fixed parameters define the position in the current design space (i.e. the level of detail), and the variable parameters set its size and allow for its exploration. After the metrics are calculated via simulation and synthesis for each set of parameters, the results are evaluated and the parameters can be adopted for the next iteration. In best case, the results indicate, how to increase the level of detail. Otherwise, the level of detail is fixed and different variable parameters are evaluated. The NoC simulation framework will soon be available via this website. Currently, we will provide the source code only on email request. If you are interested, please contact Jan Moritz Joseph.

Latency Reductions in NoCs via adaptive prioritization of semi-static data streams

SemiStaticDataStreamSemiStaticDataStreamWe proposed a novel prioritization technique to reduce latencies in Network-on-chips. For individual routers, we adaptively allocate default paths assuming that subsequent packages are part of a data stream and, thus, routing decisions are identical. Since proactive routing to an output port is performed, the conventional router pipeline is partly bypassed. The method is deterministic, non-speculative with local and autonomous decisions, retains the standard network load, and does not penalize non-prioritized links. Virtual point-to-point connections emerge, which span multiple hops and accelerate interleaved streams. We achieve an average package latency reduction of 4.8% to 12.2% in simulations for PARSEC benchmarks. This work was published in 2016:

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