Otto-von-Guericke-Universität Magdeburg

 
 
 
 
 
 
 
 

Publikationen

2017

Begutachteter Zeitschriftenartikel
Joseph, Jan Moritz;  Blochwitz, Christopher;  García Ortiz, Alberto;  Pionteck, Thilo 

Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs$Jan Moritz Joseph, ChristopherBlochwitz, Alberto García-Ortiz, Thilo Piontecka
In: Microprocessors and microsystems - Amsterdam [u.a.]: Elsevier, Bd. 48.2017, S. 36-47; http://dx.doi.org/10.1016/j.micpro.2016.09.011

Buchbeitrag
Drewes, Tobias;  Joseph, Jan Moritz;  Pionteck, Thilo 

An FPGA-based prototyping framework for networks-on-Chip
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; poster session A]

Blochwitz, Christopher;  Klink, Raphael;  Joseph, Jan Moritz;  Pionteck, Thilo 

Contentious live-tracing as debugging approach on FPGAS
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; General session]

Joseph, Jan Moritz;  Bamberg, Lennart;  Wrieden, Sven;  Ermel, Dominik;  García-Oritz, Alberto;  Pionteck, Thilo 

Design method for asymmetric 3D interconnect architectures with high level models
In: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017): July 12-14, 2017, Madrid, Spain : proceedings - [Piscataway, NJ]: IEEE, insges. 8 S.; http://dx.doi.org/10.1109/recosoc.2017.8016143 ; [Symposium: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2017, Madrid, Spain, July 12-14 2017]

Joseph, Jan Moritz;  Mey, Morten;  Ehlers, Kristian;  Blochwitz, Christopher;  Winker, Tobias;  Pionteck, Thilo 

Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; Poster session B]

Blochwitz, Christopher;  Wolff, Julian;  Joseph, Jan Moritz;  Werner, Stefan;  Heinrich, Dennis;  Groppe, Sven;  Pionteck, Thilo 

Hardware-accelerated radix-tree based string sorting for big data applications
In: Architecture of Computing Systems - ARCS 2017: 30th International Conference, Vienna, Austria, April 3-6, 2017, Proceedings - Cham: Springer International Publishing, S. 47-58 - (Lecture Notes in Computer Science; 10172); http://dx.doi.org/10.1007/978-3-319-54999-6_4 ; [Konferenz: 30th International Conference on Architecture of Computing Systems, ARCS 2017, Vienna, Austria, April 3-6, 2017]

2016

Buchbeitrag
Joseph, Jan Moritz;  Wrieden, Sven;  Blochwitz, Christopher;  Garcia-Oritz, Alberto;  Pionteck, Thilo 

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip
In: 2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoc) : June 27-29, 2016, Tallinn, Estonia. - Piscataway, NJ : IEEEPublikationslink   

Joseph, Jan Moritz;  Blochwitz, Christioher;  Pionteck, Thilo 

Adaptive allocation of default router paths in Network-on-Chips for latency reduction
In: 2016 International Conference on High Performance Computing & Simulation (HPCS). - Piscataway, NJ : IEEEPublikationslink   

Joseph, Jan Moritz;  Winker, Tobias;  Ehlers, Christian;  Blochwitz, Christopher;  Pionteck, Thilo 

Hardware-accelerated pose estimation for embedded systems using vivado HLS
In: ReConFig : 2016 International Conference on Reconfigurable Computing and FPGAs : November 30 - December 2, Cancun, Mexico. - Piscataway, NJ : IEEE ; [Kongress: 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig, Cancun, Mexico, November 30 - December 2, 2016]

2015

Herausgeberschaft
Joseph, Jan Moritz;  Blochwitz, Christopher;  Pionteck, Thilo;  Garcia-Ortiz, Alberto 

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
In: 2015, S. 1-4, 10.1109/NORCHIP.2015.7364370

2014

Herausgeberschaft
Joseph, Jan Moritz;  Pionteck, Thilo 

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling
In: 2014, S. 1-6, 10.1109/ISSOC.2014.6972440

Letzte Änderung: 24.03.2017 - Ansprechpartner: Dipl.-Ing. Arno Krüger